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this document contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing speci?ations for the mpc860 family. this document contains the following topics: topic page part i, ?verview 1 part ii, ?eatures 2 part iii, ?aximum tolerated ratings 6 part iv, ?hermal characteristics 7 part v, ?ower dissipation 8 part vi, ?c characteristics 9 part vii, ?hermal calculation and measurement 10 part viii, ?ayout practices 13 part ix, ?us signal timing 13 part x, ?eee 1149.1 electrical speci?ations 41 part xi, ?pm electrical characteristics 43 part xii, ?topia ac electrical speci?ations 65 part xiii, ?ec electrical characteristics 66 part xiv, ?echanical data and ordering information 70 part xv, ?ocument revision history 74 part i overview the mpc860 quad integrated communications controller (powerquicc) is a versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. it particularly excels in both communications and networking systems. the powerquicc unit is referred to as the mpc860 in this manual. the mpc860 is a derivative of motorolas mc68360 quad integrated communications controller (quicc ), referred to here as the quicc, that implements the powerpc architecture. the cpu on the mpc860 is a 32-bit hardware speci?ation mpc860ec/d rev. 6.1, 11/2002 mpc860 family hardware speci?ations
2 mpc860 family hardware speci?ations motorola features mpc8xx core that incorporates memory management units (mmus) and instruction and data caches and that implements the powepc instruction set. the communications processor module (cpm) from the mc68360 quicc has been enhanced by the addition of the inter-integrated controller (i 2 c) channel. the memory controller has been enhanced, enabling the mpc860 to support any type of memory, including high-performance memories and new types of drams. a pcmcia socket controller supports up to two sockets. a real-time clock has also been integrated. table 1 shows the functionality supported by the members of the mpc860 family. part ii features the following list summarizes the key mpc860 features: embedded single-issue, 32-bit mpc8xx core (implementing the powerpc architecture) with thirty-two 32-bit general-purpose registers (gprs) the core performs branch prediction with conditional prefetch, without conditional execution 4- or 8-kbyte data cache and 4- or 16-kbyte instruction cache (see table 1) 16-kbyte instruction caches are four-way, set-associative with 256 sets; 4-kbyte instruction caches are two-way, set-associative with 128 sets. 8-kbyte data caches are two-way, set-associative with 256 sets; 4-kbyte data caches are two-way, set-associative with 128 sets. cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. table 1. mpc860 family functionality part cache (kbytes) ethernet atm scc ref. 1 1 supporting documentation for these devices refers to the following: 1. mpc860 powerquicc users manual (mpc860um/d, rev. 1). 2. mpc8xx atm supplement (mpc860sarum/ad). 3. mpc860t (rev. d), fast ethernet controller supplement (mpc860trevdsupp). 4. MPC855t users manual (MPC855tum/d, rev. 1). instruction cache data cache 10t 10/100 mpc860de 4 4 up to 2 2 1 mpc860dt 4 4 up to 2 1 yes 2 1,2,3 mpc860dp 16 8 up to 2 1 yes 2 1,2,3 mpc860en 4 4 up to 4 4 1 mpc860sr 4 4 up to 4 ? yes 4 1,2 mpc860t 4 4 up to 4 1 yes 4 1,2,3 mpc860p 16 8 up to 4 1 yes 4 1,2,3 MPC855t 4 4 1 1 yes 1 4
motorola mpc860 family hardware speci?ations 3 features caches are physically addressed, implement a least recently used (lru) replacement algorithm, and are lockable on a cache block basis. instruction and data caches are two-way, set-associative, physically addressed, lru replacement, and lockable on-line granularity. mmus with 32-entry tlb, fully associative instruction, and data tlbs mmus support multiple page sizes of 4, 16, and 512 kbytes, and 8 mbytes; 16 virtual address spaces and 16 protection groups advanced on-chip-emulation debug mode up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines operates at up to 80 mhz memory controller (eight banks) contains complete dynamic ram (dram) controller each bank can be a chip select or ras to support a dram bank up to 15 wait states programmable per memory bank glueless interface to dram, simms, sram, eprom, flash eprom, and other memory devices. dram controller programmable to support most size and speed memory interfaces four cas lines, four we lines, one oe line boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) variable block sizes (32 kbyte to 256 mbyte) selectable write protection on-chip bus arbitration logic general-purpose timers four 16-bit timers or two 32-bit timers gate mode can enable/disable counting interrupt can be masked on reference match and event capture system integration unit (siu) bus monitor software watchdog periodic interrupt timer (pit) low-power stop mode clock synthesizer
4 mpc860 family hardware speci?ations motorola features decrementer, time base, and real-time clock (rtc) from the powerpc architecture reset controller ieee 1149.1 test access port (jtag) interrupts seven external interrupt request (irq) lines 12 port pins with interrupt capability 23 internal interrupt sources programmable priority between sccs programmable highest priority request 10/100 mbps ethernet support, fully compliant with the ieee 802.3u standard (not available when using atm over utopia interface) atm support compliant with atm forum uni 4.0 speci?ation cell processing up to 50?0 mbps at 50-mhz system clock cell multiplexing/demultiplexing support of aal5 and aal0 protocols on a per-vc basis. aal0 support enables oam and software implementation of other protocols). atm pace control (apc) scheduler, providing direct support for constant bit rate (cbr) and unspeci?d bit rate (ubr) and providing control mechanisms enabling software support of available bit rate (abr) physical interface support for utopia (10/100-mbps is not supported with this interface) and byte-aligned serial (for example, t1/e1/adsl) utopia-mode atm supports level-1 master with cell-level handshake, multi-phy (up to 4 physical layer devices), connection to 25-, 51-, or 155-mbps framers, and utopia/system clock ratios of 1/2 or 1/3. serial-mode atm connection supports transmission convergence (tc) function for t1/e1/adsl lines; cell delineation; cell payload scrambling/descrambling; automatic idle/unassigned cell insertion/stripping; header error control (hec) generation, checking, and statistics. communications processor module (cpm) risc communications processor (cp) communication-speci? commands (for example, graceful stop transmit , enter hunt mode , and restart transmit ) supports continuous mode transmission and reception on all serial channels up to 8kbytes of dual-port ram 16 serial dma (sdma) channels
motorola mpc860 family hardware speci?ations 5 features three parallel i/o registers with open-drain capability four baud-rate generators (brgs) independent (can be connected to any scc or smc) allow changes during operation autobaud support option four serial communications controllers (sccs) ethernet/ieee 802.3 optional on scc1?, supporting full 10-mbps operation (available only on specially programmed devices). hdlc/sdlc (all channels supported at 2 mbps) hdlc bus (implements an hdlc-based local area network (lan)) asynchronous hdlc to support ppp (point-to-point protocol) appletalk universal asynchronous receiver transmitter (uart) synchronous uart serial infrared (irda) binary synchronous communication (bisync) totally transparent (bit streams) totally transparent (frame based with optional cyclic redundancy check (crc)) two smcs (serial management channels) uart transparent general circuit interface (gci) controller can be connected to the time-division multiplexed (tdm) channels one spi (serial peripheral interface) supports master and slave modes supports multimaster operation on the same bus one i 2 c (inter-integrated circuit) port supports master and slave modes multiple-master environment support time-slot assigner (tsa) allows sccs and smcs to run in multiplexed and/or non-multiplexed operation supports t1, cept, pcm highway, isdn basic rate, isdn primary rate, user de?ed 1- or 8-bit resolution
6 mpc860 family hardware speci?ations motorola maximum tolerated ratings allows independent transmit and receive routing, frame synchronization, clocking allows dynamic changes can be internally connected to six serial channels (four sccs and two smcs) parallel interface port (pip) centronics interface support supports fast connection between compatible ports on the mpc860 or the mc68360 pcmcia interface master (socket) interface, release 2.1 compliant supports two independent pcmcia sockets eight memory or i/o windows supported low power support full on?ll units fully powered doze?ore functional units disabled, except time base decrementer, pll, memory controller, rtc, and cpm in low-power standby sleep?ll units disabled, except rtc and pit, pll active for fast wake up deep sleep?ll units disabled including pll, except rtc and pit power down mode?all units powered down, except pll, rtc, pit, time base, and decrementer debug interface eight comparators: four operate on instruction address, two operate on data address, and two operate on data supports conditions: = <> each watchpoint can generate a break-point internally 3.3 v operation with 5-v ttl compatibility except extal and extclk 357-pin ball grid array (bga) package part iii maximum tolerated ratings this section provides the maximum tolerated voltage and temperature ranges for the mpc860. table 3-2 provides the maximum ratings. this device contains circuitry protecting against damage due to high-static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced, if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v dd ).
motorola mpc860 family hardware speci?ations 7 thermal characteristics part iv thermal characteristics table 4-3 shows the thermal characteristics for the mpc860. table 3-2. maximum tolerated ratings (gnd = 0 v) rating symbol value unit supply voltage 1 1 the power supply of the device must start its ramp from 0.0 v. v ddh ?.3 to 4.0 v v ddl ?.3 to 4.0 v kapwr ?.3 to 4.0 v vddsyn ?.3 to 4.0 v input voltage 2 2 functional operating conditions are provided with the dc electrical speci?ations in table 6-5. absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. caution : all inputs that tolerate 5 v cannot be more than 2.5 v greater than the supply voltage. this restriction applies to power-up and normal operation (that is, if the mpc860 is unpowered, voltage greater than 2.5 v must not be applied to its inputs). v in gnd ?0.3 to vddh v temperature 3 (standard) 3 minimum temperatures are guaranteed as ambient temperature, t a . maximum temperatures are guaranteed as junction temperature, t j . t a(min) 0?c t j(max) 95 ?c temperature 3 (extended) t a(min) ?0 ?c t j(max) 95 ?c storage temperature range t stg ?5 to 150 ?c table 4-3. mpc860 thermal resistance data rating environment symbol rev a rev b, c, d unit junction to ambient 1 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air ?w, power dissipation of other components on the board, and board thermal resistance. natural convection single layer board (1s) r ja 2 31 40 ?/w four layer board (2s2p) r jma 3 20 25 air flow (200 ft/min) single layer board (1s) r jma 3 26 32 four layer board (2s2p) r jma 3 16 21 junction to board 4 r jb 815 junction to case 5 r jc 57 junction to package top 6 natural convection jt 12 air flow (200 ft/min) 2 3
8 mpc860 family hardware speci?ations motorola power dissipation part v power dissipation table 5-4 provides power dissipation information. the modes are 1:1, where cpu and bus speeds are equal, and 2:1 mode, where cpu frequency is twice bus speed. note values in table 5-4?represent v ddl -based power dissipation and do not include i/o power dissipation over v ddh . i/o power dissipation varies widely by application due to buffer current, depending on external circuitry. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3 per jedec jesd51-6 with the board horizontal. 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. for exposed pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. table 5-4. power dissipation (p d ) die revision frequency (mhz) typical 1 1 typical power dissipation is measured at 3.3 v. maximum 2 2 maximum power dissipation is measured at 3.5 v. unit a.3 and previous 25 450 550 mw 40 700 850 mw 50 870 1050 mw b.1 and c.1 33 375 tbd mw 50 575 tbd mw 66 750 tbd mw d.3 and d.4 (1:1 mode) 50 656 735 mw 66 tbd tbd mw d.3 and d.4 (2:1 mode) 66 722 762 mw 80 851 909 mw
motorola mpc860 family hardware speci?ations 9 dc characteristics part vi dc characteristics table 6-5 provides the dc electrical characteristics for the mpc860. table 6-5. dc electrical speci?ations characteristic symbol min max unit operating voltage at 40 mhz or less v ddh , v ddl , vddsyn 3.0 3.6 v kapwr (power-down mode) 2.0 3.6 v kapwr (all other operating modes) v ddh ?0.4 v ddh v operating voltage greater than 40 mhz v ddh , v ddl , kapwr, vddsyn 3.135 3.465 v kapwr (power-down mode) 2.0 3.6 v kapwr (all other operating modes) v ddh ?0.4 v ddh v input high voltage (all inputs except extal and extclk) v ih 2.0 5.5 v input low voltage v il gnd 0.8 v extal, extclk input high voltage v ihc 0.7 (v ddh )v ddh + 0.3 v input leakage current, v in = 5.5 v (except tms, trst , dsck, and dsdi pins) i in 100 ? input leakage current, v in = 3.6 v (except tms, trst , dsck, and dsdi pins) i in ?0a input leakage current, v in = 0 v (except tms, trst , dsck, and dsdi pins) i in ?0a input capacitance 1 1 input capacitance is periodically sampled. c in ?0pf output high voltage, i oh = ?.0 ma, v ddh = 3.0 v (except xtal, xfc, and open drain pins) v oh 2.4 v output low voltage iol = 2.0 ma, clkout iol = 3.2 ma 2 iol = 5.3 ma 3 iol = 7.0 ma, txd1/pa14, txd2/pa12 iol = 8.9 ma, ts , t a , tea , bi , bb , hreset , sreset v ol 0.5 v
10 mpc860 family hardware speci?ations motorola thermal calculation and measurement part vii thermal calculation and measurement for the following discussions, p d = (v dd i dd ) + pi/o, where pi/o is the power dissipation of the i/o drivers. 7.1 estimation with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , in ? can be obtained from the equation: t j = t a + (r ja p d ) where: t a = ambient temperature (?) r ja = package junction-to-ambient thermal resistance (?/w) p d = power dissipation in package the junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance. however, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity t j ? t a ) are possible. 7.2 estimation with junction-to-case thermal resistance historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca 2 a(0:31), tsiz0/reg , tsiz1, d(0:31), dp(0:3)/irq (3:6), rd/wr , b urst , rsv /irq2 , ip_b(0:1)/iwp(0:1)/ vfls(0:1), ip_b2/iois16_b/at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/vf1, ip_b6/dsdi/at0, ip_b7/ptr/at3, rxd1 /pa15, rxd2/pa13, l1txdb/pa11, l1rxdb/pa10, l1txda/pa9, l1rxda/pa8, tin1/l1rclka/brgo1/clk1/pa7, brgclk1/t out1 /clk2/pa6, tin2/l1tclka/brgo2/clk3/pa5, t out2 /clk4/pa4, tin3/brgo3/clk5/pa3, brgclk2/l1rclkb/t out3 /clk6/pa2, tin4/brgo4/clk7/ pa1, l1tclkb/t out4 /clk8/pa0, rejct1 /spisel /pb31, spiclk/pb30, spimosi/pb29, brgo4/spimiso/ pb28, brgo1/i2csda/pb27, brgo2/i2cscl/pb26, smtxd1/pb25, smrxd1/pb24, smsyn1 /sd a ck1 / pb23, smsyn2 /sd a ck2 /pb22, smtxd2/l1clkob/pb21, smrxd2/l1clkoa/pb20, l1st1/r ts1 /pb19, l1st2/r ts2 /pb18, l1st3/l1rqb /pb17, l1st4/l1rqa /pb16, brgo3/pb15, rstr t1 /pb14, l1st1/r ts1 / dreq0 /pc15, l1st2/r ts2 /dreq1 /pc14, l1st3/l1rqb /pc13, l1st4/l1rqa /pc12, cts1 /pc11, tga te1 /cd1 /pc10, cts2 /pc9, tga te2 /cd2 /pc8, sd a ck2 /l1tsyncb/pc7, l1rsyncb/pc6, sd a ck1 / l1tsynca/pc5, l1rsynca/pc4, pd15, pd14, pd13, pd12, pd11, pd10, pd9, pd8, pd5, pd6, pd7, pd4, pd3, mii_mdc, mii_tx_er, mii_en, mii_mdio, mii_txd[0:3]. 3 bdip /gpl_b (5), br , bg , frz/irq6 , cs (0:5), cs (6)/ce (1)_b, cs (7)/ce (2)_b, we0 /bs _b0/iord , we1 /bs _b1/io wr , we2 /bs _b2/pcoe , we3 /bs _b3/pcwe , bs _a(0:3), gpl_a0 /gpl_b0 , oe /gpl_a1 / gpl_b1 , gpl_a (2:3)/gpl_b (2:3)/cs (2:3), upwaita/gpl_a4 , upwaitb/gpl_b4 , gpl_a5 , ale_a, ce 1_a, ce 2_a, ale_b/dsck/at1, op(0:1), op2/modck1/sts , op3/modck2/dsdo, baddr(28:30).
motorola mpc860 family hardware speci?ations 11 estimation with junction-to-board thermal resistance where: r ja = junction-to-ambient thermal resistance (?/w) r jc = junction-to-case thermal resistance (?/w) r ca = case-to-ambient thermal resistance (?/w) r jc is device related and cannot be in?enced by the user. the user adjusts the thermal environment to affect the case-to-ambient thermal resistance, r ca . for instance, the user can change the air ?w around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat ?ws through the case and the heat sink to the ambient environment. for most packages, a better model is required. 7.3 estimation with junction-to-board thermal resistance a simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. the junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. it has been observed that the thermal performance of most plastic packages and especially pbga packages is strongly dependent on the board temperature; see figure 7-1. figure 7-1. effect of board temperature rise on thermal behavior 0 10 20 30 40 50 60 70 80 90 100 0 20406080 board temperture rise above ambient divided by package junction temperature rise above ambient divided by package power board temperature rise above ambient divided by package power junction temperature rise above ambient divided by package power
12 mpc860 family hardware speci?ations motorola estimation using simulation if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b + (r jb p d ) where: r jb = junction-to-board thermal resistance (?/w) t b = board temperature (?) p d = power dissipation in package if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 estimation using simulation when the board temperature is not known, a thermal simulation of the application is needed. the simple two resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. 7.5 experimental determination to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) where: jt = thermal characterization parameter t t = thermocouple temperature on top of package p d = power dissipation in package the thermal characterization parameter is measured per jedec jesd51-2 speci?ation using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed ?t against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
motorola mpc860 family hardware speci?ations 13 references 7.6 references semiconductor equipment and materials international (415) 964-5111 805 east middle?ld rd mountain view, ca 94043 mil-spec and eia/jesd (jedec) speci?ations 800-854-7179 or (available from global engineering documents) 303-397-7956 jedec speci?ations http://www.jedec.org 1. 1. c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module,?proceedings of semitherm, san diego, 1998, pp. 47 54. 2. 2. b. joiner and v. adams, ?easurement and simulation of junction to board thermal resistance and its application in thermal modeling,?proceedings of semitherm, san diego, 1999, pp. 212 220. part viii layout practices each v dd pin on the mpc860 should be provided with a low-impedance path to the boards supply. each gnd pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v dd power supply should be bypassed to ground using at least four 0.1 ?-bypass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v dd and gnd should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the mpc860 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and re?ctions caused by these fast output switching times. this recommendation particularly applies to the address and data busses. maximum pc trace lengths of 6 inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. part ix bus signal timing table 9-6 provides the bus operation timing for the mpc860 at 33, 40, 50, and 66 mhz. the maximum bus speed supported by the mpc860 is 66 mhz. higher-speed parts must be operated in half-speed bus mode (for example, an mpc860 used at 80 mhz must be con?ured for a 40 mhz bus).
14 mpc860 family hardware speci?ations motorola bus signal timing the timing for the mpc860 bus shown assumes a 50-pf load for maximum delays and a 0-pf load for minimum delays. table 9-6. bus operation timings num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max b1 clkout period 30.30 30.30 25.00 30.30 20.00 30.30 15.15 30.30 ns b1a extclk to clkout phase skew (extclk > 15 mhz and mf <= 2) ?.90 0.90 ?.90 0.90 ?.90 0.90 ?.90 0.90 ns b1b extclk to clkout phase skew (extclk > 10 mhz and mf < 10) ?.30 2.30 ?.30 2.30 ?.30 2.30 ?.30 2.30 ns b1c clkout phase jitter (extclk > 15 mhz and mf <= 2) 1 ?.60 0.60 ?.60 0.60 ?.60 0.60 ?.60 0.60 ns b1d clkout phase jitter 1 ?.00 2.00 ?.00 2.00 ?.00 2.00 ?.00 2.00 ns b1e clkout frequency jitter (mf < 10) 1 0.50 0.50 0.50 0.50 % b1f clkout frequency jitter (10 < mf < 500) 1 2.00 2.00 2.00 2.00 % b1g clkout frequency jitter (mf > 500) 1 3.00 3.00 3.00 3.00 % b1h frequency jitter on extclk 2 0.50 0.50 0.50 0.50 % b2 clkout pulse width low 12.12 10.00 8.00 6.06 ns b3 clkout width high 12.12 10.00 8.00 6.06 ns b4 clkout rise time 3 4.00 4.00 4.00 4.00 ns b5 33 clkout fall time 3 4.00 4.00 4.00 4.00 ns b7 clkout to a(0:31), baddr(28:30), rd/wr , b urst , d(0:31), dp(0:3) invalid 7.58 6.25 5.00 3.80 ns b7a clkout to tsiz(0:1), reg , rsv , at(0:3), bdip , ptr invalid 7.58 6.25 5.00 3.80 ns b7b clkout to br , bg , frz, vfls(0:1), vf(0:2) iwp(0:2), lwp(0:1), sts invalid 4 7.58 6.25 5.00 3.80 ns b8 clkout to a(0:31), baddr(28:30) rd/wr , b urst , d(0:31), dp(0:3) valid 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b8a clkout to tsiz(0:1), reg , rsv , at(0:3) bdip , ptr valid 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b8b clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid 4 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b9 clkout to a(0:31), baddr(28:30), rd/wr , b urst , d(0:31), dp(0:3), tsiz(0:1), reg , rsv , at(0:3), ptr high-z 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns
motorola mpc860 family hardware speci?ations 15 bus signal timing b11 clkout to ts , bb assertion 7.58 13.58 6.25 12.25 5.00 11.00 3.80 11.29 ns b11a clkout to t a , bi assertion (when driven by the memory controller or pcmcia interface) 2.50 9.25 2.50 9.25 2.50 9.25 2.50 9.75 ns b12 clkout to ts , bb negation 7.58 14.33 6.25 13.00 5.00 11.75 3.80 8.54 ns b12a clkout to t a , bi negation (when driven by the memory controller or pcmcia interface) 2.50 11.00 2.50 11.00 2.50 11.00 2.50 9.00 ns b13 clkout to ts , bb high-z 7.58 21.58 6.25 20.25 5.00 19.00 3.80 14.04 ns b13a clkout to t a , bi high-z (when driven by the memory controller or pcmcia interface) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b14 clkout to tea assertion 2.50 10.00 2.50 10.00 2.50 10.00 2.50 9.00 ns b15 clkout to tea high-z 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b16 t a , bi valid to clkout (setup time) 9.75 9.75 9.75 6.00 ns b16a tea , kr , retr y , cr valid to clkout (setup time) 10.00 10.00 10.00 4.50 ns b16b bb , bg , br , valid to clkout (setup time) 5 8.50 8.50 8.50 4.00 ns b17 clkout to t a , tea , bi , bb , bg , br valid (hold time) 1.00 1.00 1.00 2.00 ns b17a clkout to kr , retr y , cr valid (hold time) 2.00 2.00 2.00 2.00 ns b18 d(0:31), dp(0:3) valid to clkout rising edge (setup time) 6 6.00 6.00 6.00 6.00 ns b19 clkout rising edge to d(0:31), dp(0:3) valid (hold time) 6 1.00 1.00 1.00 2.00 ns b20 d(0:31), dp(0:3) valid to clkout falling edge (setup time) 7 4.00 4.00 4.00 4.00 ns b21 clkout falling edge to d(0:31), dp(0:3) valid (hold time) 7 2.00 2.00 2.00 2.00 ns b22 clkout rising edge to cs asserted gpcm acs = 00 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b22a clkout falling edge to cs asserted gpcm acs = 10, trlx = 0 8.00 8.00 8.00 8.00 ns b22b clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 0 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns table 9-6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
16 mpc860 family hardware speci?ations motorola bus signal timing b22c clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 1 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns b23 clkout rising edge to cs negated gpcm read access, gpcm write access acs = 00, trlx = 0, and csnt = 0 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns b24 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 0 5.58 4.25 3.00 1.79 ns b24a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 0 13.15 10.50 8.00 5.58 ns b25 clkout rising edge to oe , we (0:3) asserted 9.00 9.00 9.00 9.00 ns b26 clkout rising edge to oe negated 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns b27 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 1 35.88 29.25 23.00 16.94 ns b27a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 1 43.45 35.50 28.00 20.73 ns b28 clkout rising edge to we (0:3) negated gpcm write access csnt = 0 9.00 9.00 9.00 9.00 ns b28a clkout falling edge to we (0:3) negated gpcm write access trlx = 0, csnt = 1, ebdf = 0 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b28b clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1, acs = 10, or acs = 11, ebdf = 0 14.33 13.00 11.75 10.54 ns b28c clkout falling edge to we (0:3) negated gpcm write access trlx = 0, csnt = 1 write access trlx = 0, csnt = 1, ebdf = 1 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns b28d clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1, acs = 10, or acs = 11, ebdf = 1 17.99 16.00 14.13 12.31 ns b29 we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access csnt = 0, ebdf = 0 5.58 4.25 3.00 1.79 ns b29a we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 0 13.15 10.5 8.00 5.58 ns table 9-6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
motorola mpc860 family hardware speci?ations 17 bus signal timing b29b cs negated to d(0:31), dp(0:3), high-z gpcm write access, acs = 00, trlx = 0, and csnt = 0 5.58 4.25 3.00 1.79 ns b29c cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, acs = 10, or acs = 11, ebdf = 0 13.15 10.5 8.00 5.58 ns b29d we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 0 43.45 35.5 28.00 20.73 ns b29e cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10, or acs = 11, ebdf = 0 43.45 35.5 28.00 29.73 ns b29f we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 1 8.86 6.88 5.00 3.18 ns b29g cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 0, csnt = 1, acs = 10, or acs = 11, ebdf = 1 8.86 6.88 5.00 3.18 ns b29h we (0:3) negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 1 38.67 31.38 24.50 17.83 ns b29i cs negated to d(0:31), dp(0:3) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10, or acs = 11, ebdf = 1 38.67 31.38 24.50 17.83 ns b30 cs , we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access 8 5.58 4.25 3.00 1.79 ns b30a we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm, write access, trlx = 0, csnt = 1, cs negated to a(0:31) invalid gpcm write access, trlx = 0, csnt =1 acs = 10, or acs = 11, ebdf = 0 13.15 10.50 8.00 5.58 ns b30b we (0:3) negated to a(0:31), invalid gpcm baddr(28:30) invalid gpcm write access, trlx = 1, csnt = 1. cs negated to a(0:31), invalid gpcm, write access, trlx = 1, csnt = 1, acs = 10, or acs = 11, ebdf = 0 43.45 35.50 28.00 20.73 ns table 9-6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
18 mpc860 family hardware speci?ations motorola bus signal timing b30c we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx = 0, csnt = 1. cs negated to a(0:31) invalid gpcm write access, trlx = 0, csnt = 1, acs = 10, acs = 11, ebdf = 1 8.36 6.38 4.50 2.68 ns b30d we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx = 1, csnt =1. cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10, or acs = 11, ebdf = 1 38.67 31.38 24.50 17.83 ns b31 clkout falling edge to cs valid?s requested by control bit cst4 in the corresponding word in upm 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b31a clkout falling edge to cs valid?s requested by control bit cst1 in the corresponding word in upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b31b clkout rising edge to cs valid?s requested by control bit cst2 in the corresponding word in upm 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b31c clkout rising edge to cs valid?s requested by control bit cst3 in the corresponding word in upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns b31d clkout falling edge to cs valid?s requested by control bit cst1 in the corresponding word in upm, ebdf = 1 13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns b32 clkout falling edge to bs valid?s requested by control bit bst4 in the corresponding word in upm 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b32a clkout falling edge to bs valid?s requested by control bit bst1 in the corresponding word in upm, ebdf = 0 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b32b clkout rising edge to bs valid?s requested by control bit bst2 in the corresponding word in upm 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b32c clkout rising edge to bs valid?s requested by control bit bst3 in the corresponding word in upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b32d clkout falling edge to bs valid?s requested by control bit bst1 in the corresponding word in upm, ebdf = 1 13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns table 9-6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
motorola mpc860 family hardware speci?ations 19 bus signal timing b33 clkout falling edge to gpl valid?s requested by control bit gxt4 in the corresponding word in upm 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b33a clkout rising edge to gpl valid?s requested by control bit gxt3 in the corresponding word in upm 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns b34 a(0:31), baddr(28:30), and d(0:31) to cs valid?s requested by control bit cst4 in the corresponding word in upm 5.58 4.25 3.00 1.79 ns b34a a(0:31), baddr(28:30), and d(0:31) to cs valid?s requested by control bit cst1 in the corresponding word in upm 13.15 10.50 8.00 5.58 ns b34b a(0:31), baddr(28:30), and d(0:31) to cs valid?s requested by control bit cst2 in the corresponding word in upm 20.73 16.75 13.00 9.36 ns b35 a(0:31), baddr(28:30) to cs valid?s requested by control bit bst4 in the corresponding word in upm 5.58 4.25 3.00 1.79 ns b35a a(0:31), baddr(28:30), and d(0:31) to bs valid?s requested by control bit bst1 in the corresponding word in upm 13.15 10.50 8.00 5.58 ns b35b a(0:31), baddr(28:30), and d(0:31) to bs valid?s requested by control bit bst2 in the corresponding word in upm 20.73 16.75 13.00 9.36 ns b36 a(0:31), baddr(28:30), and d(0:31) to gpl valid?s requested by control bit gxt4 in the corresponding word in upm 5.58 4.25 3.00 1.79 ns b37 upwait valid to clkout falling edge 9 6.00 6.00 6.00 6.00 ns b38 clkout falling edge to upwait valid 9 1.00 1.00 1.00 1.00 ns b39 as valid to clkout rising edge 10 7.00 7.00 7.00 7.00 ns b40 a(0:31), tsiz(0:1), rd/wr , b urst , valid to clkout rising edge 7.00 7.00 7.00 7.00 ns table 9-6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
20 mpc860 family hardware speci?ations motorola bus signal timing figure 9-2 is the control timing diagram. b41 ts valid to clkout rising edge (setup time) 7.00 7.00 7.00 7.00 ns b42 clkout rising edge to ts valid (hold time) 2.00 2.00 2.00 2.00 ns b43 as negation to memory controller signals negation tbd tbd tbd tbd ns 1 phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value. 2 if the rate of change of the frequency of extal is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then the maximum allowed jitter on extal can be up to 2%. 3 the timings speci?d in b4 and b5 are based on full strength clock. 4 the timing for br output is relevant when the mpc860 is selected to work with external bus arbiter. the timing for bg output is relevant when the mpc860 is selected to work with internal bus arbiter. 5 the timing required for br input is relevant when the mpc860 is selected to work with internal bus arbiter. the timing for bg input is relevant when the mpc860 is selected to work with external bus arbiter. 6 the d(0:31) and dp(0:3) input timings b18 and b19 refer to the rising edge of the clkout in which the t a input signal is asserted. 7 the d(0:31) and dp(0:3) input timings b20 and b21 refer to the falling edge of the clkout. this timing is valid only for read accesses controlled by chip-selects under control of the upm in the memory controller, for data beats where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout.) 8 the timing b30 refers to cs when acs = 00 and to we (0:3) when csnt = 0. 9 the signal upwait is considered asynchronous to the clkout and synchronized internally. the timings speci?d in b37 and b38 are speci?d to enable the freeze of the upm output signals as described in figure 9-17. 10 the as signal is considered asynchronous to the clkout. the timing b39 is speci?d in order to allow the behavior speci?d in figure 9-20. table 9-6. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
motorola mpc860 family hardware speci?ations 21 bus signal timing figure 9-2. control timing figure 9-3 provides the timing for the external clock. figure 9-3. external clock timing clkout outputs a b 2.0 v 0.8 v 0.8 v 2.0 v 2.0 v 0.8 v 2.0 v 0.8 v outputs 2.0 v 0.8 v 2.0 v 0.8 v b a inputs 2.0 v 0.8 v 2.0 v 0.8 v d c inputs 2.0 v 0.8 v 2.0 v 0.8 v c d a maximum output delay specification. b minimum output hold time. c minimum input setup time specification. d minimum input hold time specification. clkout b1 b5 b3 b4 b1 b2
22 mpc860 family hardware speci?ations motorola bus signal timing figure 9-4 provides the timing for the synchronous output signals. figure 9-4. synchronous output signals timing figure 9-5 provides the timing for the synchronous active pull-up and open-drain output signals. figure 9-5. synchronous active pull-up resistor and open-drain outputs signals timing clkout output signals output signals output signals b8 b7 b9 b8a b9 b7a b8b b7b clkout ts , bb t a , bi tea b13 b12 b11 b11a b12a b13a b15 b14
motorola mpc860 family hardware speci?ations 23 bus signal timing figure 9-6 provides the timing for the synchronous input signals. figure 9-6. synchronous input signals timing figure 9-7 provides normal case timing for input data. it also applies to normal read accesses under the control of the upm in the memory controller. figure 9-7. input data timing in normal case figure 9-8 provides the timing for the input data controlled by the upm for data beats where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout.) clkout t a , bi tea , kr , retr y , cr bb , bg , br b16 b17 b16a b17a b16b b17 clkout t a d[0:31], dp[0:3] b16 b17 b19 b18
24 mpc860 family hardware speci?ations motorola bus signal timing figure 9-8. input data timing when controlled by upm in the memory controller and dlt3 = 1 figure 9-9 through figure 9-12 provide the timing for the external bus read controlled by various gpcm factors. figure 9-9. external bus read timing (gpcm controlled?cs = 00) clkout t a d[0:31], dp[0:3] b20 b21 clkout a[0:31] cs x oe we [0:3] ts d[0:31], dp[0:3] b11 b12 b23 b8 b22 b26 b19 b18 b25 b28
motorola mpc860 family hardware speci?ations 25 bus signal timing figure 9-10. external bus read timing (gpcm controlled?rlx = 0, acs = 10) figure 9-11. external bus read timing (gpcm controlled?rlx = 0, acs = 11) clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b23 b26 b19 b18 b25 b24 clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b22b b8 b22c b23 b24a b25 b26 b19 b18
26 mpc860 family hardware speci?ations motorola bus signal timing figure 9-12. external bus read timing (gpcm controlled?rlx = 1, acs = 10, acs = 11) figure 9-13 through figure 9-15 provide the timing for the external bus write controlled by various gpcm factors. clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b27 b27a b22b b22c b19 b18 b26 b23
motorola mpc860 family hardware speci?ations 27 bus signal timing figure 9-13. external bus write timing (gpcm controlled?rlx = 0, csnt = 0) clkout a[0:31] cs x we [0:3] oe ts d[0:31], dp[0:3] b11 b8 b22 b23 b12 b30 b28 b25 b26 b8 b9 b29 b29b
28 mpc860 family hardware speci?ations motorola bus signal timing figure 9-14. external bus write timing (gpcm controlled?rlx = 0, csnt = 1) b23 b30a b30c clkout a[0:31] cs x oe we [0:3] ts d[0:31], dp[0:3] b11 b8 b22 b12 b28b b28d b25 b26 b8 b28a b9 b28c b29c b29g b29a b29f
motorola mpc860 family hardware speci?ations 29 bus signal timing figure 9-15. external bus write timing (gpcm controlled?rlx = 1, csnt = 1) figure 9-16 provides the timing for the external bus controlled by the upm. b23 b22 b8 b12 b11 clkout a[0:31] cs x we [0:3] ts oe d[0:31], dp[0:3] b30d b30b b28b b28d b25 b29e b29i b26 b29d b29h b28a b28c b9 b8 b29b
30 mpc860 family hardware speci?ations motorola bus signal timing figure 9-16. external bus timing (upm controlled signals) figure 9-17 provides the timing for the asynchronous asserted upwait signal controlled by the upm. clkout cs x b31d b8 b31 b34 b32b gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] a[0:31] b31c b31b b34a b32 b32a b32d b34b b36 b35b b35a b35 b33 b32c b33a b31a
motorola mpc860 family hardware speci?ations 31 bus signal timing figure 9-17. asynchronous upwait asserted detection in upm handled cycles timing figure 9-18 provides the timing for the asynchronous negated upwait signal controlled by the upm. figure 9-18. asynchronous upwait negated detection in upm handled cycles timing figure 9-19 provides the timing for the synchronous external master access controlled by the gpcm. clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] b37 b38 clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] b37 b38
32 mpc860 family hardware speci?ations motorola bus signal timing figure 9-19. synchronous external master access timing (gpcm handled acs = 00) figure 9-20 provides the timing for the asynchronous external master memory access controlled by the gpcm. figure 9-20. asynchronous external master memory access timing (gpcm controlled?cs = 00) figure 9-21 provides the timing for the asynchronous external master control signals negation. clkout ts a[0:31], tsiz[0:1], r/w , b urst cs x b41 b42 b40 b22 clkout as a[0:31], tsiz[0:1], r/w cs x b39 b40 b22
motorola mpc860 family hardware speci?ations 33 bus signal timing figure 9-21. asynchronous external master?ontrol signals negation timing table 9-7 provides interrupt timing for the mpc860. figure 9-22 provides the interrupt detection timing for the external level-sensitive lines. figure 9-22. interrupt detection timing for external level sensitive lines figure 9-23 provides the interrupt detection timing for the external edge-sensitive lines. table 9-7. interrupt timing num characteristic 1 1 the timings i39 and i40 describe the testing conditions under which the irq lines are tested when being de?ed as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clkout. the timings i41, i42, and i43 are speci?d to allow the correct function of the irq lines detection circuitry, and has no direct relation with the total system interrupt latency that the mpc860 is able to support. all frequencies unit min max i39 irq x valid to clkout rising edge (setup time) 6.00 ns i40 irq x hold time after clkout 2.00 ns i41 irq x pulse width low 3.00 ns i42 irq x pulse width high 3.00 ns i43 irq x edge-to-edge time 4 t clockout as cs x, we [0:3], oe , gplx , bs [0:3] b43 clkout irq x i39 i40
34 mpc860 family hardware speci?ations motorola bus signal timing figure 9-23. interrupt detection timing for external edge sensitive lines table 9-8 shows the pcmcia timing for the mpc860. table 9-8. pcmcia timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max p44 a(0:31), reg valid to pcmcia strobe asserted 1 20.73 16.75 13.00 9.36 ns p45 a(0:31), reg valid to ale negation 1 28.30 23.00 18.00 13.15 ns p46 clkout to reg valid 7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84 ns p47 clkout to reg invalid 8.58 7.25 6.00 4.84 ns p48 clkout to ce1 , ce2 asserted 7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84 ns p49 clkout to ce1 , ce2 negated 7.58 15.58 6.25 14.25 5.00 13.00 3.79 11.84 ns p50 clkout to pcoe , iord , pcwe , io wr assert time 11.00 11.00 11.00 11.00 ns p51 clkout to pcoe , iord , pcwe , io wr negate time 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns p52 clkout to ale assert time 7.58 15.58 6.25 14.25 5.00 13.00 3.79 10.04 ns p53 clkout to ale negate time 15.58 14.25 13.00 11.84 ns p54 pcwe , io wr negated to d(0:31) invalid 1 5.58 4.25 3.00 1.79 ns p55 w ait a and w aitb valid to clkout rising edge 1 8.00 8.00 8.00 8.00 ns p56 clkout rising edge to w ait a and w aitb invalid 1 2.00 2.00 2.00 2.00 ns clkout irq x i41 i42 i43 i43
motorola mpc860 family hardware speci?ations 35 bus signal timing figure 9-24 provides the pcmcia access cycle timing for the external bus read. figure 9-24. pcmcia access cycles timing external bus read figure 9-25 provides the pcmcia access cycle timing for the external bus write. 1 psst = 1. otherwise add psst times cycle time. psht = 0. otherwise add psht times cycle time. these synchronous timings de?e when the w aitx signals are detected in order to freeze (or relieve) the pcmcia current cycle. the w aitx assertion will be effective only if it is detected 2 cycles before the psl timer expiration. see pcmcia interface in the mpc860 powerquicc user s manual . clkout a[0:31] reg ce1 /ce2 pcoe , iord ts d[0:31] ale b19 b18 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47
36 mpc860 family hardware speci?ations motorola bus signal timing figure 9-25. pcmcia access cycles timing external bus write figure 9-26 provides the pcmcia w ait signals detection timing. figure 9-26. pcmcia w ait signals detection timing table 9-9 shows the pcmcia port timing for the mpc860. clkout a[0:31] reg ce1 /ce2 cwe , io wr ts d[0:31] ale b9 b8 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 p54 clkout w ait x p55 p56
motorola mpc860 family hardware speci?ations 37 bus signal timing figure 9-27 provides the pcmcia output port timing for the mpc860. figure 9-27. pcmcia output port timing figure 9-28 provides the pcmcia output port timing for the mpc860. figure 9-28. pcmcia input port timing table 9-10 shows the debug port timing for the mpc860. table 9-9. pcmcia port timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max p57 clkout to opx valid 19.00 19.00 19.00 19.00 ns p58 hreset negated to opx drive 1 1 op2 and op3 only. 25.73 21.75 18.00 14.36 ns p59 ip_xx valid to clkout rising edge 5.00 5.00 5.00 5.00 ns p60 clkout rising edge to ip_xx invalid 1.00 1.00 1.00 1.00 ns clkout hreset output signals op2, op3 p57 p58 clkout input signals p59 p60
38 mpc860 family hardware speci?ations motorola bus signal timing figure 9-29 provides the input timing for the debug port clock. figure 9-29. debug port clock input timing figure 9-30 provides the timing for the debug port. figure 9-30. debug port timings table 9-10. debug port timing num characteristic all frequencies unit min max p61 dsck cycle time 3 t clockout p62 dsck clock pulse width 1.25 t clockout p63 dsck rise and fall times 0.00 3.00 ns p64 dsdi input data setup time 8.00 ns p65 dsdi data hold time 5.00 ns p66 dsck low to dsdo data valid 0.00 15.00 ns p67 dsck low to dsdo invalid 0.00 2.00 ns dsck d61 d61 d63 d62 d62 d63 dsck dsdi dsdo d64 d65 d66 d67
motorola mpc860 family hardware speci?ations 39 bus signal timing table 9-11 shows the reset timing for the mpc860. figure 9-31 shows the reset timing for the data bus con?uration. table 9-11. reset timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max r69 clkout to hreset high impedance 20.00 20.00 20.00 20.00 ns r70 clkout to sreset high impedance 20.00 20.00 20.00 20.00 ns r71 rstconf pulse width 515.15 425.00 340.00 257.58 ns r72 r73 con?uration data to hreset rising edge setup time 504.55 425.00 350.00 277.27 ns r74 con?uration data to rstconf rising edge setup time 350.00 350.00 350.00 350.00 ns r75 con?uration data hold time after rstconf negation 0.00 0.00 0.00 0.00 ns r76 con?uration data hold time after hreset negation 0.00 0.00 0.00 0.00 ns r77 hreset and rstconf asserted to data out drive 25.00 25.00 25.00 25.00 ns r78 rstconf negated to data out high impedance 25.00 25.00 25.00 25.00 ns r79 clkout of last rising edge before chip three-state hreset to data out high impedance 25.00 25.00 25.00 25.00 ns r80 dsdi, dsck setup 90.91 75.00 60.00 45.45 ns r81 dsdi, dsck hold time 0.00 0.00 0.00 0.00 ns r82 sreset negated to clkout rising edge for dsdi and dsck sample 242.42 200.00 160.00 121.21 ns
40 mpc860 family hardware speci?ations motorola bus signal timing figure 9-31. reset timing?on?uration from data bus figure 9-32 provides the reset timing for the data bus weak drive during con?uration. figure 9-32. reset timing?ata bus weak drive during con?uration figure 9-33 provides the reset timing for the debug port con?uration. hreset rstconf d[0:31] (in) r71 r74 r73 r75 r76 clkout hreset d[0:31] (out) (weak) rstconf r69 r79 r77 r78
motorola mpc860 family hardware speci?ations 41 ieee 1149.1 electrical specifications figure 9-33. reset timing?ebug port con?uration part x ieee 1149.1 electrical speci?ations table 10-12 provides the jtag timings for the mpc860 shown in figure 10-34 through figure 10-37. table 10-12. jtag timing num characteristic all frequencies unit min max j82 tck cycle time 100.00 ns j83 tck clock pulse width measured at 1.5 v 40.00 ns j84 tck rise and fall times 0.00 10.00 ns j85 tms, tdi data setup time 5.00 ns j86 tms, tdi data hold time 25.00 ns j87 tck low to tdo data valid 27.00 ns j88 tck low to tdo data invalid 0.00 ns j89 tck low to tdo high impedance 20.00 ns j90 trst assert time 100.00 ns j91 trst setup time to tck low 40.00 ns j92 tck falling edge to output valid 50.00 ns j93 tck falling edge to output valid out of high impedance 50.00 ns j94 tck falling edge to output high impedance 50.00 ns j95 boundary scan input valid to tck rising edge 50.00 ns j96 tck rising edge to boundary scan input invalid 50.00 ns clkout sreset dsck, dsdi r70 r82 r80 r80 r81 r81
42 mpc860 family hardware speci?ations motorola ieee 1149.1 electrical specifications figure 10-34. jtag test clock input timing figure 10-35. jtag test access port timing diagram figure 10-36. jtag trst timing diagram tck j82 j83 j82 j83 j84 j84 tck tms, tdi tdo j85 j86 j87 j88 j89 tck trst j91 j90
motorola mpc860 family hardware speci?ations 43 cpm electrical characteristics figure 10-37. boundary scan (jtag) timing diagram part xi cpm electrical characteristics this section provides the ac and dc electrical speci?ations for the communications processor module (cpm) of the mpc860. 11.1 pip/pio ac electrical speci?ations table 11-13 provides the pip/pio ac timings as shown in figure 11-38 through figure 11-42. table 11-13. pip/pio timing num characteristic all frequencies unit min max 21 data-in setup time to stbi low 0 ns 22 data-in hold time to stbi high 2.5 ?t3 1 1 t3 = speci?ation 23. clk 23 stbi pulse width 1.5 clk 24 stbo pulse width 1 clk ?5 ns ns 25 data-out setup time to stbo low 2 clk 26 data-out hold time from stbo high 5 clk 27 stbi low to stbo low (rx interlock) 2 clk 28 stbi low to stbo high (tx interlock) 2 clk 29 data-in setup time to clock high 15 ns 30 data-in hold time from clock high 7.5 ns 31 clock low to data-out valid (cpu writes data, control, or direction) 25 ns tck output signals output signals output signals j92 j94 j93 j95 j96
44 mpc860 family hardware speci?ations motorola pip/pio ac electrical specifications figure 11-38. pip rx (interlock mode) timing diagram figure 11-39. pip tx (interlock mode) timing diagram figure 11-40. pip rx (pulse mode) timing diagram data-in stbi 23 24 22 stbo 27 21 data-out 24 23 26 28 25 stbo (output) stbi (input) data-in 23 22 21 stbi (input) stbo (output) 24
motorola mpc860 family hardware speci?ations 45 idma controller ac electrical specifications figure 11-41. pip tx (pulse mode) timing diagram figure 11-42. parallel i/o data-in/data-out timing diagram 11.2 idma controller ac electrical speci?ations table 11-14 provides the idma controller timings as shown in figure 11-43 through figure 11-46. table 11-14. idma controller timing num characteristic all frequencies unit min max 40 dreq setup time to clock high 7 ns 41 dreq hold time from clock high 3 ns 42 sd a ck assertion delay from clock high 12 ns data-out 24 26 25 stbo (output) stbi (input) 23 clko data-in 29 31 30 data-out
46 mpc860 family hardware speci?ations motorola idma controller ac electrical specifications figure 11-43. idma external requests timing diagram figure 11-44. sd a ck timing diagram?eripheral write, externally-generated t a 43 sd a ck negation delay from clock low 12 ns 44 sd a ck negation delay from t a low 20 ns 45 sd a ck negation delay from clock high 15 ns 46 t a assertion to falling edge of the clock setup time (applies to external t a ) 7ns table 11-14. idma controller timing (continued) num characteristic all frequencies unit min max 41 40 dreq (input) clko (output) data 42 46 43 clko (output) ts (output) r/w (output) t a (input) sd a ck
motorola mpc860 family hardware speci?ations 47 idma controller ac electrical specifications figure 11-45. sd a ck timing diagram?eripheral write, internally-generated t a figure 11-46. sd a ck timing diagram?eripheral read, internally-generated t a data 42 44 clko (output) ts (output) r/w (output) t a (output) sd a ck data 42 45 clko (output) ts (output) r/w (output) t a (output) sd a ck
48 mpc860 family hardware speci?ations motorola baud rate generator ac electrical specifications 11.3 baud rate generator ac electrical speci?ations table 11-15 provides the baud rate generator timings as shown in figure 11-47. figure 11-47. baud rate generator timing diagram 11.4 timer ac electrical speci?ations table 11-16 provides the general-purpose timer timings as shown in figure 11-48. table 11-15. baud rate generator timing num characteristic all frequencies unit min max 50 brgo rise and fall time 10 ns 51 brgo duty cycle 40 60 % 52 brgo cycle 40 ns table 11-16. timer timing num characteristic all frequencies unit min max 61 tin/tga te rise and fall time 10 ns 62 tin/tga te low time 1 clk 63 tin/tga te high time 2 clk 64 tin/tga te cycle time 3 clk 65 clko low to t out valid 3 25 ns 52 50 51 brgox 50 51
motorola mpc860 family hardware speci?ations 49 serial interface ac electrical specifications figure 11-48. cpm general-purpose timers timing diagram 11.5 serial interface ac electrical speci?ations table 11-17 provides the serial interface timings as shown in figure 11-49 through figure 11-53. table 11-17. si timing num characteristic all frequencies unit min max 70 l1rclk, l1tclk frequency (dsc = 0) 1, 2 syncclk/2.5 mhz 71 l1rclk, l1tclk width low (dsc = 0) 2 p + 10 ns 71a l1rclk, l1tclk width high (dsc = 0) 3 p + 10 ns 72 l1txd, l1st(1?), l1rq , l1clko rise/fall time 15.00 ns 73 l1rsync, l1tsync valid to l1clk edge (sync setup time) 20.00 ns 74 l1clk edge to l1rsync, l1tsync, invalid (sync hold time) 35.00 ns 75 l1rsync, l1tsync rise/fall time 15.00 ns 76 l1rxd valid to l1clk edge (l1rxd setup time) 17.00 ns 77 l1clk edge to l1rxd invalid (l1rxd hold time) 13.00 ns 78 l1clk edge to l1st(1?) valid 4 10.00 45.00 ns 78a l1sync valid to l1st(1?) valid 10.00 45.00 ns 79 l1clk edge to l1st(1?) invalid 10.00 45.00 ns 80 l1clk edge to l1txd valid 10.00 55.00 ns 80a l1tsync valid to l1txd valid 4 10.00 55.00 ns 81 l1clk edge to l1txd high impedance 0.00 42.00 ns 82 l1rclk, l1tclk frequency (dsc =1) 16.00 or syncclk/2 mhz clko tin/tga te (input) t out (output) 64 65 61 62 63 61 60
50 mpc860 family hardware speci?ations motorola serial interface ac electrical specifications figure 11-49. si receive timing diagram with normal clocking (dsc = 0) 83 l1rclk, l1tclk width low (dsc =1) p + 10 ns 83a l1rclk, l1tclk width high (dsc = 1) 3 p + 10 ns 84 l1clk edge to l1clko valid (dsc = 1) 30.00 ns 85 l1rq valid before falling edge of l1tsync 4 1.00 l1tcl k 86 l1gr setup time 2 42.00 ns 87 l1gr hold time 42.00 ns 88 l1clk edge to l1sync valid (fsd = 00) cnt = 0000, byt = 0, dsc = 0) 0.00 ns 1 the ratio syncclk/l1rclk must be greater than 2.5/1. 2 these specs are valid for idl mode only. 3 where p = 1/clkout. thus, for a 25-mhz clko1 rate, p = 40 ns. 4 these strobes and txd on the ?st bit of the frame become valid after l1clk edge or l1sync, whichever is later. table 11-17. si timing (continued) num characteristic all frequencies unit min max l1rxd (input) l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1st(4-1) (output) 71 72 70 71a rfsd=1 75 73 74 77 78 76 79 bit0
motorola mpc860 family hardware speci?ations 51 serial interface ac electrical specifications figure 11-50. si receive timing with double-speed clocking (dsc = 1) l1rxd (input) l1rclk (fe=1, ce=1) (input) l1rclk (fe=0, ce=0) (input) l1rsync (input) l1st(4-1) (output) 72 rfsd=1 75 73 74 77 78 76 79 83a 82 l1clko (output) 84 bit0
52 mpc860 family hardware speci?ations motorola serial interface ac electrical specifications figure 11-51. si transmit timing diagram (dsc = 0) l1txd (output) l1tclk (fe=0, ce=0) (input) l1tclk (fe=1, ce=1) (input) l1tsync (input) l1st(4-1) (output) 71 70 72 73 75 74 80a 80 78 tfsd=0 81 79 bit0
motorola mpc860 family hardware speci?ations 53 serial interface ac electrical specifications figure 11-52. si transmit timing with double speed clocking (dsc = 1) l1txd (output) l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1st(4-1) (output) 72 tfsd=0 75 73 74 78a 80 79 83a 82 l1clko (output) 84 bit0 78 81
54 mpc860 family hardware speci?ations motorola serial interface ac electrical specifications figure 11-53. idl timing b17 b16 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b15 l1rxd (input) l1txd (output) l1st(4-1) (output) l1rq (output) 73 77 123456789 10 11 12 13 14 15 16 17 18 19 20 74 80 b17 b16 b15 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m 71 71 l1gr (input) 78 85 72 76 87 86 l1rsync (input) l1rclk (input) 81
motorola mpc860 family hardware speci?ations 55 scc in nmsi mode electrical specifications 11.6 scc in nmsi mode electrical speci?ations table 11-18 provides the nmsi external clock timing. table 11-19 provides the nmsi internal clock timing. figure 11-54 through figure 11-56 show the nmsi timings. table 11-18. nmsi external clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk1 width high 1 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater than or equal to 2.25/1. 1/syncclk ns 101 rclk1 and tclk1 width low 1/syncclk + 5 ns 102 rclk1 and tclk1 rise/fall time 15.00 ns 103 txd1 active delay (from tclk1 falling edge) 0.00 50.00 ns 104 r ts1 active/inactive delay (from tclk1 falling edge) 0.00 50.00 ns 105 cts1 setup time to tclk1 rising edge 5.00 ns 106 rxd1 setup time to rclk1 rising edge 5.00 ns 107 rxd1 hold time from rclk1 rising edge 2 2 also applies to cd and cts hold time when they are used as an external sync signal. 5.00 ns 108 cd1 setup time to rclk1 rising edge 5.00 ns table 11-19. nmsi internal clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk1 frequency 1 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 3/1. 0.00 syncclk/3 mhz 102 rclk1 and tclk1 rise/fall time ns 103 txd1 active delay (from tclk1 falling edge) 0.00 30.00 ns 104 r ts1 active/inactive delay (from tclk1 falling edge) 0.00 30.00 ns 105 cts1 setup time to tclk1 rising edge 40.00 ns 106 rxd1 setup time to rclk1 rising edge 40.00 ns 107 rxd1 hold time from rclk1 rising edge 2 2 also applies to cd and cts hold time when they are used as an external sync signals. 0.00 ns 108 cd1 setup time to rclk1 rising edge 40.00 ns
56 mpc860 family hardware speci?ations motorola scc in nmsi mode electrical specifications figure 11-54. scc nmsi receive timing diagram figure 11-55. scc nmsi transmit timing diagram rclk1 cd1 (input) 102 100 107 108 107 rxd1 (input) cd1 (sync input) 102 101 106 tclk1 cts1 (input) 102 100 104 107 txd1 (output) cts1 (sync input) 102 101 r ts1 (output) 105 103 104
motorola mpc860 family hardware speci?ations 57 ethernet electrical specifications figure 11-56. hdlc bus timing diagram 11.7 ethernet electrical speci?ations table 11-20 provides the ethernet timings as shown in figure 11-57 through figure 11-61. table 11-20. ethernet timing num characteristic all frequencies unit min max 120 clsn width high 40 ns 121 rclk1 rise/fall time 15 ns 122 rclk1 width low 40 ns 123 rclk1 clock period 1 80 120 ns 124 rxd1 setup time 20 ns 125 rxd1 hold time 5 ns 126 rena active delay (from rclk1 rising edge of the last data bit) 10 ns 127 rena width low 100 ns 128 tclk1 rise/fall time 15 ns 129 tclk1 width low 40 ns 130 tclk1 clock period 1 99 101 ns 131 txd1 active delay (from tclk1 rising edge) 10 50 ns 132 txd1 inactive delay (from tclk1 rising edge) 10 50 ns 133 tena active delay (from tclk1 rising edge) 10 50 ns tclk1 cts1 (echo input) 102 100 104 txd1 (output) 102 101 r ts1 (output) 103 104 107 105
58 mpc860 family hardware speci?ations motorola ethernet electrical specifications figure 11-57. ethernet collision timing diagram figure 11-58. ethernet receive timing diagram 134 tena inactive delay (from tclk1 rising edge) 10 50 ns 135 rstr t active delay (from tclk1 falling edge) 10 50 ns 136 rstr t inactive delay (from tclk1 falling edge) 10 50 ns 137 reject width low 1 clk 138 clko1 low to sd a ck asserted 2 ?0ns 139 clko1 low to sd a ck negated 2 ?0ns 1 the ratios syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 2/1. 2 sd a ck is asserted whenever the sdma writes the incoming frame da into memory. table 11-20. ethernet timing (continued) num characteristic all frequencies unit min max clsn(cts1 ) 120 (input) rclk1 121 rxd1 (input) 121 rena(cd1 ) (input) 125 124 123 127 126 last bit
motorola mpc860 family hardware speci?ations 59 ethernet electrical specifications figure 11-59. ethernet transmit timing diagram figure 11-60. cam interface receive start timing diagram figure 11-61. cam interface reject timing diagram tclk1 128 txd1 (output) 128 tena(r ts1 ) (input) notes: transmit clock invert (tci) bit in gsmr is set. if rena is deasserted before tena, or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of the frame transmission. 1. 2. rena(cd1 ) (input) 133 134 132 131 121 129 (note 2) rclk1 rxd1 (input) rstr t (output) 0 136 125 1 1 bit1 bit2 start frame reject 137
60 mpc860 family hardware speci?ations motorola smc transparent ac electrical specifications 11.8 smc transparent ac electrical speci?ations table 11-21 provides the smc transparent timings as shown in figure 11-62. figure 11-62. smc transparent timing diagram 11.9 spi master ac electrical speci?ations table 11-22 provides the spi master timings as shown in figure 11-63 and figure 11-64. table 11-21. smc transparent timing num characteristic all frequencies unit min max 150 smclk clock period 1 1 syncclk must be at least twice as fast as smclk. 100 ns 151 smclk width low 50 ns 151a smclk width high 50 ns 152 smclk rise/fall time 15 ns 153 smtxd active delay (from smclk falling edge) 10 50 ns 154 smrxd/smsync setup time 20 ns 155 rxd1/smsync hold time 5 ns smclk smrxd (input) 152 150 smtxd (output) 152 151 smsync 151 154 153 155 154 155 note note: this delay is equal to an integer number of character-length clocks. 1.
motorola mpc860 family hardware speci?ations 61 spi master ac electrical specifications figure 11-63. spi master (cp = 0) timing diagram table 11-22. spi master timing num characteristic all frequencies unit min max 160 master cycle time 4 1024 t cyc 161 master clock (sck) high or low time 2 512 t cyc 162 master data setup time (inputs) 50 ns 163 master data hold time (inputs) 0 ns 164 master data valid (after sck edge) 20 ns 165 master data hold time (outputs) 0 ns 166 rise time output 15 ns 167 fall time output 15 ns spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) 162 data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164
62 mpc860 family hardware speci?ations motorola spi slave ac electrical specifications figure 11-64. spi master (cp = 1) timing diagram 11.10spi slave ac electrical speci?ations table 11-23 provides the spi slave timings as shown in figure 11-65 and figure 11-66. table 11-23. spi slave timing num characteristic all frequencies unit min max 170 slave cycle time 2 t cyc 171 slave enable lead time 15 ns 172 slave enable lag time 15 ns 173 slave clock (spiclk) high or low time 1 t cyc 174 slave sequential transfer delay (does not require deselect) 1 t cyc 175 slave data setup time (inputs) 20 ns 176 slave data hold time (inputs) 20 ns 177 slave access time 50 ns spimosi (output) spiclk (ci=0) (output) spiclk (ci=1) (output) spimiso (input) data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 162
motorola mpc860 family hardware speci?ations 63 spi slave ac electrical specifications figure 11-65. spi slave (cp = 0) timing diagram figure 11-66. spi slave (cp = 1) timing diagram spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 173 173 170 msb lsb msb 181 177 182 175 179 spisel (input) 171 172 174 data msb lsb msb undef 181 178 176 182 spimosi (input) spiclk (ci=0) (input) spiclk (ci=1) (input) spimiso (output) 180 data 181 182 msb lsb 181 177 182 175 179 spisel (input) 174 data msb lsb undef 178 176 182 msb msb 172 173 173 171 170 181
64 mpc860 family hardware speci?ations motorola i2c ac electrical specifications 11.11i 2 c ac electrical speci?ations table 11-24 provides the i 2 c (scl < 100 khz) timings. table 11-25 provides the i 2 c (scl > 100 khz) timings. table 11-24. i 2 c timing (scl < 100 kh z ) num characteristic all frequencies unit min max 200 scl clock frequency (slave) 0 100 khz 200 scl clock frequency (master) 1 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3 pre_scaler 2). the ratio syncclk/(brgclk / pre_scaler) must be greater or equal to 4/1. 1.5 100 khz 202 bus free time between transmissions 4.7 s 203 low period of scl 4.7 s 204 high period of scl 4.0 s 205 start condition setup time 4.7 s 206 start condition hold time 4.0 s 207 data hold time 0 s 208 data setup time 250 ns 209 sdl/scl rise time 1 s 210 sdl/scl fall time 300 ns 211 stop condition setup time 4.7 s table 11-25. . i 2 c timing (scl > 100 kh z ) num characteristic expression all frequencies unit min max 200 scl clock frequency (slave) fscl 0 brgclk/48 hz 200 scl clock frequency (master) 1 fscl brgclk/16512 brgclk/48 hz 202 bus free time between transmissions 1/(2.2 * fscl) s 203 low period of scl 1/(2.2 * fscl) s 204 high period of scl 1/(2.2 * fscl) s 205 start condition setup time 1/(2.2 * fscl) s 206 start condition hold time 1/(2.2 * fscl) s 207 data hold time 0 s 208 data setup time 1/(40 * fscl) s 209 sdl/scl rise time 1/(10 * fscl) s 210 sdl/scl fall time 1/(33 * fscl) s 211 stop condition setup time 1/2(2.2 * fscl) s
motorola mpc860 family hardware speci?ations 65 utopia ac electrical specifications figure 11-67 shows the i 2 c bus timing. figure 11-67. i 2 c bus timing diagram part xii utopia ac electrical speci?ations table 12-26 shows the ac electrical speci?ations for the utopia interface. figure 12-68 shows signal timings during utopia receive operations. 1 scl frequency is given by scl = brgclk_frequency / ((brg register + 3) pre_scaler 2). the ratio syncclk/(brgclk / pre_scaler) must be greater or equal to 4/1. table 12-26. utopia ac electrical speci?ations num signal characteristic direction min max unit u1 utpclk rise/fall time (internal clock option) output 3.5 ns duty cycle 50 50 % frequency 50 mhz u1a utpclk rise/fall time (external clock option) input 3.5 ns duty cycle 40 60 % frequency 50 mhz u2 rxenb and txenb active delay output 2 16 ns u3 utpb, soc, rxclav and txclav setup time input 8 ns u4 utpb, soc, rxclav and txclav hold time input 1 ns u5 utpb, soc active delay (and phreq and phsel active delay in mphy mode) output 2 16 ns scl 202 205 203 207 204 208 206 209 211 210 sda
66 mpc860 family hardware speci?ations motorola fec electrical characteristics figure 12-68. utopia receive timing figure 12-69 shows signal timings during utopia transmit operations. figure 12-69. utopia transmit timing part xiii fec electrical characteristics this section provides the ac electrical speci?ations for the fast ethernet controller (fec). note that the timing speci?ations for the mii signals are independent of system clock frequency (part speed designation). also, mii signals use ttl signal levels compatible with devices operating at either 5.0 v or 3.3 v. utpclk utpb rxenb u1 3 2 soc 4 rxclav phreq n 3 4 highz at mphy highz at mphy u1 u5 u3 u4 u4 u3 u2 utpclk utpb txenb 1 2 soc 5 txclav phsel n 3 4 5 highz at mphy highz at mphy u1 u1 u5 u5 u2 u3 u4
motorola mpc860 family hardware speci?ations 67 mii receive signal timing (mii_rxd[3:0], mii_rx_dv, mii_rx_er, mii_rx_clk) 13.1 mii receive signal timing (mii_rxd[3:0], mii_rx_dv, mii_rx_er, mii_rx_clk) the receiver functions correctly up to a mii_rx_clk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed the mii_rx_clk frequency ?1%. table 13-27 provides information on the mii receive signal timing. figure 13-70 shows mii receive signal timing. figure 13-70. mii receive signal timing diagram 13.2 mii transmit signal timing (mii_txd[3:0], mii_tx_en, mii_tx_er, mii_tx_clk) the transmitter functions correctly up to a mii_tx_clk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed the mii_tx_clk frequency ?1%. table 13-28 provides information on the mii transmit signal timing. table 13-27. mii receive signal timing num characteristic min max unit m1 mii_rxd[3:0], mii_rx_dv, mii_rx_er to mii_rx_clk setup 5 ns m2 mii_rx_clk to mii_rxd[3:0], mii_rx_dv, mii_rx_er hold 5 ns m3 mii_rx_clk pulse width high 35% 65% mii_rx_clk period m4 mii_rx_clk pulse width low 35% 65% mii_rx_clk period m1 m2 mii_rx_clk (input) mii_rxd[3:0] (inputs) mii_rx_dv mii_rx_er m3 m4
68 mpc860 family hardware speci?ations motorola mii async inputs signal timing (mii_crs, mii_col) figure 13-71 shows the mii transmit signal timing diagram. figure 13-71. mii transmit signal timing diagram 13.3 mii async inputs signal timing (mii_crs, mii_col) table 13-29 provides information on the mii async inputs signal timing. figure 13-72 shows the mii asynchronous inputs signal timing diagram. figure 13-72. mii async inputs timing diagram table 13-28. mii transmit signal timing num characteristic min max unit m5 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er invalid 5 ns m6 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er valid 25 m7 mii_tx_clk pulse width high 35 65% mii_tx_clk period m8 mii_tx_clk pulse width low 35% 65% mii_tx_clk period table 13-29. mii async inputs signal timing num characteristic min max unit m9 mii_crs, mii_col minimum pulse width 1.5 mii_tx_clk period m6 mii_tx_clk (input) mii_txd[3:0] (outputs) mii_tx_en mii_tx_er m5 m7 m8 mii_crs, mii_col m9
motorola mpc860 family hardware speci?ations 69 mii serial management channel timing (mii_mdio, mii_mdc) 13.4 mii serial management channel timing (mii_mdio, mii_mdc) table 13-30 provides information on the mii serial management channel signal timing. the fec functions correctly with a maximum mdc frequency in excess of 2.5 mhz. the exact upper bound is under investigation. figure 13-73 shows the mii serial management channel timing diagram. figure 13-73. mii serial management channel timing diagram table 13-30. mii serial management channel timing num characteristic min max unit m10 mii_mdc falling edge to mii_mdio output invalid (minimum propagation delay) 0ns m11 mii_mdc falling edge to mii_mdio output valid (max prop delay) 25 ns m12 mii_mdio (input) to mii_mdc rising edge setup 10 ns m13 mii_mdio (input) to mii_mdc rising edge hold 0 ns m14 mii_mdc pulse width high 40% 60% mii_mdc period m15 mii_mdc pulse width low 40% 60% mii_mdc period m11 mii_mdc (output) mii_mdio (output) m12 m13 mii_mdio (input) m10 m14 mm15
70 mpc860 family hardware speci?ations motorola mechanical data and ordering information part xiv mechanical data and ordering information table 14-31 provides information on the mpc860 revision d.3 and d.4 derivative devices. table 14-32 identi?s the packages and operating frequencies available for the mpc860. table 14-31. mpc860 family revision d.3 and d.4 derivatives device number of sccs 1 1 serial communications controller (scc). ethernet support 2 (mbps) 2 up to 4 channels at 40 mhz or 2 channels at 25 mhz. multi-channel hdlc support atm support MPC855t 1 10/100 yes yes mpc860de 2 10 n/a n/a mpc860dt 10/100 yes yes mpc860dp 10/100 yes yes mpc860en 4 10 n/a n/a mpc860sr 10 yes yes mpc860t 10/100 yes yes mpc860p 10/100 yes yes table 14-32. mpc860 family package/frequency availability package type frequency (mhz) temperature (tj) order number
motorola mpc860 family hardware speci?ations 71 mechanical data and ordering information table 14-33 identi?s the packages and operating frequencies available for the mpc860p. ball grid array (zp suf?) 50 0?to 95? xpc860dezp50nn 1 xpc860dtzp50nn xpc860enzp50nn xpc860srzp50nn xpc860tzp50nn xpc855tzp50d4 66 0?to 95? xpc860dezp66nn xpc860dtzp66nn xpc860enzp66nn xpc860srzp66nn xpc860tzp66nn xpc855tzp66d4 80 0?to 95? xpc860dezp80nn xpc860dtzp80nn xpc860enzp80nn xpc860srzp80nn xpc860tzp80nn xpc855tzp80d4 ball grid array (czp suf?) 50 ?0?to 95? xpc860deczp50nn xpc860dtczp50nn xpc860enczp50nn xpc860srczp50nn xpc860tczp50nn xpc855tczp50d4 66 ?0?to 95? xpc860deczp66nn xpc860dtczp66nn xpc860enczp66nn xpc860srczp66nn xpc860tczp66nn xpc855tczp66d4 1 where nn speci?s version d.3 (as d3) or d.4 (as d4). table 14-33. mpc860p package/frequency availability package type frequency (mhz) temperature (tj) order number ball grid array (zp suf?) 50 0?to 95? xpc860dpzp50nn 1 xpc860pzp50nn 1 where nn speci?s version d.3 (as d3) or d.4 (as d4). 66 0?to 95? xpc860dpzp66nn xpc860pzp66nn 80 0?to 95? xpc860dpzp80nn xpc860pzp80nn ball grid array (czp suf?) 50 ?0?to 95? xpc860dpczp50nn xpc860pczp50nn 66 ?0?to 95? xpc860dpczp66nn xpc860pczp66nn table 14-32. mpc860 family package/frequency availability (continued)
72 mpc860 family hardware speci?ations motorola pin assignments 14.1 pin assignments figure 14-74 shows the top view pinout of the pbga package. for additional information, see the mpc860 powerquicc users manual , or the MPC855t users manual . note: this is the top view of the device. figure 14-74. pinout of the pbga package pd3 irq7 d0 d4 d1 d2 d3 d5 vddl d6 d7 d29 clkout ipa3 dp2 a2 a7 a14 a27 a29 a30 a28 a31 vddl bsa2 we1 we3 ce2a cs1 cs4 a5 a11 18 16 141312111098765 32 4 17 15 1 19 a1 a6 a13 a17 a21 a23 a22 tsiz0 bsa3 m_crs we2 gpla2 ce1a wr cs5 a4 a10 gplb4 a0 pa15 a3 a12 a16 a20 a24 a26 tsiz1 bsa1 we0 gpla1 gpla3 cs0 t a cs7 pb31 a9 gpla4 pb30 pc14 pc15 n/c n/c a15 a19 a25 a18 bsa0 gpla0 n/c cs6 gpla5 bdip cs2 pa14 a8 tea pb28 pc13 pb29 vddh vddh bi bg cs3 pa13 bb pb27 pc12 vddl gnd gnd ts irq3 vddl pa12 b urst pb26 tms pa11 irq6 ipb4 br tdo ipb3 trst m_mdio tck irq2 ipb0 m_col tdi ipb7 vddl pb24 pb25 ipb1 ipb2 ipb5 pa10 aleb pc11 pa9 pb21 gnd ipb6 alea baddr30 pb23 irq4 pc10 pc9 pb20 as op1 op0 pa 8 modck1 pb22 pc8 pc7 baddr28 baddr29 modck2 pa 6 vddl pa 7 pa5 pb16 texp extclk hreset pb18 extal pb19 pb17 vddl gnd r s t c o n f s r e s e t vddl pa3 gnd xtal pa 4 pa2 pd12 vddh w a i t _a p o r e s e t w a i t _b pb15 vddh kapwr pc6 pc5 pd11 vddh d12 d17 d9 d15 d22 d25 d31 ipa6 ipa0 ipa7 xfc ipa1 pc4 pd7 vddsyn pa 1 pb14 pd4 irq1 d8 d23 d11 d16 d19 d21 d26 d30 ipa5 ipa2 n/c ipa4 pd15 pd5 vsssyn pa 0 pd13 pd6 irq0 d13 d27 d10 d14 d18 d20 d24 d28 dp1 dp0 n/c dp3 pd9 m_tx_en vsssyn1 pd14 b a c d e f g h j k l m n p r t u v w pd10 pd8
motorola mpc860 family hardware speci?ations 73 mechanical dimensions of the pbga package 14.2 mechanical dimensions of the pbga package for more information on the printed circuit board layout of the pbga package, including thermal via design and suggested pad layout, please refer to motorola application note, plastic ball grid array (order number: an1231/d), available from your local motorola sales of?e. figure 14-75 shows the mechanical dimensions of the pbga package. figure 14-75. mechanical dimensions and bottom surface nomenclature of the pbga package w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 side view bottom view 18x 4x 357x b top view a2 a3 e 0.3 m c d a a1 d2 0.15 m c e e2 0.2 c a b 0.2 d1 e1 ab 0.25 c 0.35 c c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum c. dim min max millimeters a --- 2.05 0.50 0.70 a2 0.95 1.35 a3 0.70 0.90 b 0.60 0.90 d 25.00 bsc d1 22.86 bsc d2 22.40 22.60 e 1.27 bsc e 25.00 bsc e1 22.86 bsc e2 22.40 22.60 a1 case no. 1103-01
74 mpc860 family hardware speci?ations motorola document revision history part xv document revision history table 15-34 lists signi?ant changes between revisions of this document. table 15-34. document revision history revision date change 5.1 11/2001 revised template format, removed references to mac functionality, changed table 9-6 b23 max value @ 66 mhz from 2ns to 8ns, added this revision history table 6 10/2002 added the MPC855t. corrected figure 9-25 on page 36. 6.1 11/2002 corrected utopia rxenb* and txenb* timing values. changed incorrect usage of vcc to vdd. corrected dual port ram to 8kbytes.
motorola mpc860 family hardware speci?ations 75 document revision history this page intentionally left blank
mpc860ec/d how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625 attn: risc applications engineering information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical parameters which may be provided in motorola data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark of?e. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/af?mative action employer. ?motorola, inc. 2002

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